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november 2012 doc id 023243 rev 1 1/26 AN4121 application note poly-phase demonstration kit with the stpmc1 and stpms2 introduction this application note describes the poly-phase demonstration kit with the stpmc1 and stpms2. the stpmc1 is a metering assp implemented in an advanced 0.35 m bcd6 technology. the stpmc1 device works as an energy calculator in power line systems utilizing a rogowski coil, current transformer, shunt or hall current sensors. used in combination with one or more stpms2 ics, it implements all the functions needed in a 1-, 2- or 3-phase energy meter, providing effective measurement of active and reactive energies, v rms , i rms , instantaneous voltage and current per phase in 1-, 2- or 3-phase wye and delta services, from 2 to 4 wires. in a standalone configuration, the stpmc1 outputs a pulse train signal having a frequency proportional to the cumulative active power, and it can directly drive a stepper motor, therefore implementing a simple active energy meter. this device can also be coupled with a microprocessor for multifunction energy meters. in this case, measured data are read at a fixed time interval from the device internal registers by the microcontroller through an spi interface. the stpms2 is an assp designed to be the building block for single or multiphase energy meters. it consists of a preamplifier and two 2 nd order modulators, band-gap voltage reference, a low-drop voltage regulator and dc buffers in its analog section and clock generator and output multiplexer in its digital section. the demonstration kit is made up of a main board with the stpmc1 onboard (steval- ipe0010v1), and it can be coupled with up to 5 daughterboards, each having an stpms2 onboard to sense the voltage and current of each phase (steval-ipe0014v1). figure 1. demonstration kit block diagram am12798v1 n r s t current sensor vol t age sensor stpm s2 stpms2 stpms2 stpms2 stpm c1 dar das dah clk xtal1 xtal2 vss vssa mop mon votp vcc dan dat vdd sda- td scl- nc syn- np scs led s t p m s m m 2 s t p m s m m 2 s t p m s m m 2 p1 dar dat dan dah das www.st.com
AN4121 contents doc id 023243 rev 1 2/26 contents 1 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 motherboard circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 daughterboard circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 current sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.2 anti-aliasing filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.3 voltage sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.4 jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 clock management network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 communication with microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 layout rules for three-phase systems design . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 motherboard layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 daughterboard layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 three-phase energy measurement accuracy . . . . . . . . . . . . . . . . . . . . . . 12 4.1.1 test with symmetrical voltages and balanced load at pf = 1 . . . . . . . . 12 4.1.2 test with symmetrical voltages and balanced load at pf = 0.5 inductive and pf = 0. 8 capacitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 typical phase energy measurement accuracy . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 test with symmetrical voltages and only one phase load at pf = 1 and pf = 0,5 inductive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 appendix a three-phase systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 a.1 power in three-phase ac circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 a.2 power measurement techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 a.2.1 two-wattmeter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 a.2.2 three-wattmeter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 a.2.3 one-wattmeter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 appendix b bom list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AN4121 contents doc id 023243 rev 1 3/26 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AN4121 application description doc id 023243 rev 1 4/26 1 application description poly-phase systems, and particularly three-phase meters, are most commonly used in practical industrial applications, and in a few cases also for domestic use. the purpose of the steval-ipe0010v1 + steval-ipe0014v1 is stpmc1 and stpms2 device demonstration but it can also be used as a starting point to design a class 0.2 accuracy meter for power line systems from 2- to 4-wire delta or wye service. each phase is monitored from an independent daughterboard, in which an autonomous power supply provides the supply to the board itself and, once it is connected, also to the motherboard. in this board, the stpms2 device senses the phase current through a ct sensor, and the phase voltage through a voltage divider. the presence of a dedicated network reduces, for a large amount, the sampling (aliasing) noise, therefore increasing the meter precision. the stpms2 outputs a sigma-delta stream sent, together with supply voltage, to the stpmc1 through a card edge connector. the motherboard receives from the daughterboards the sigma-delta streams that are further elaborated by the stpmc1. this device, from a 4.194 mhz crystal oscillator, provides a common clock with programmable frequency to all the daughterboards. the motherboard, through a 10-pin flat cable connector (p1 in figure 2 ), can be interfaced to a microprocessor board to implement advanced metering features (multi-tariff, data management and storage, communication?). it also has stepper motor connectors for a simple energy meter implementation (w2, w5 in figure 2 ). the stpmc1 board can also be interfaced to a dedicated gui through the stpmxx parallel programmer/reader released with the application. table 1. operating conditions condition value unit v nom 230 v rms i nom ct: i nom = 1 a rms i max ct: i max = 30 a rms f lin 50/60 10% hz t op - 40 / + 8 5c
AN4121 circuit description doc id 023243 rev 1 5/26 2 circuit description 2.1 motherboard circuit the motherboard consists of the following sections: stpmc1 circuitry connectors. the schematic of the board is shown in figure 2 and in figure 3 . figure 2. stpmc1 circuitry schematics v c c v c c v c c v c c v c c v c c v c c d a r d a s d a t c l k d a n d a h c l k n c l k r 6 1 4 . 7 k u 8 s t p m c 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 m o n m o p s c s v d d v s s v c c v o t p d a h d a r d a s d a t d a n c l k v s s a s y n c l k i n c l k o u t s c l n l c s d a t d l e d r 6 2 4 . 7 k d a t w 3 4 1 2 w 2 m o n w 5 m o p y 1 4 1 9 4 . 3 0 4 k h z p 1 1 5 9 1 0 8 6 4 2 3 7 u 9 a s t _ m 7 4 h c 1 4 1 2 r 5 6 1 0 0 d 7 + c 6 6 1 0 0 0 u r 1 6 1 0 0 c 6 3 1 t p 2 c 6 1 1 5 p c 6 4 1 0 n r 1 5 1 0 0 d a n r 6 0 4 . 7 k c 6 5 1 0 0 n d 1 0 d a h r 3 5 1 0 0 d 1 1 r 6 3 4 . 7 k c l k d 8 d 1 2 r 5 5 1 0 0 u 9 g s t _ m 7 4 h c 1 4 7 1 4 g n d v c c c 6 2 1 5 p r 6 4 1 m 1 % d a r w 8 g n d d 9 d a s am12744v1
AN4121 circuit description doc id 023243 rev 1 6/26 figure 3. motherboard connectors schematics 2.2 daughterboard circuit this section explains the implementation of each phase network which performs the power measurement. the schematic can be divided into the following subsets: current sensing circuit (1) or (2) anti-aliasing filter (3) voltage sensing circuit (4). 2.2.1 current sensing circuit the stpms2 has an external current sensing circuit using either a current transformer, in which a burden resistor is used to produce a voltage between cin and cip proportional to the current measured, or a shunt resistor, or a rogowski coil current sensor. 2.2.2 anti-aliasing filter the anti-aliasing filter is a low-pass filter. it has a negligible influence on the voltage drop between cin and cip, vin and vip; its aim is to reduce the distortion caused by the sampling, also called aliasing, by removing the out-of-band frequencies of the input signal before sampling it with the analog-to-digital converter. filtering is easily implemented with a resistor-capacitor (rc) single-pole circuit which obtains an attenuation of - 20 db/dec. 2.2.3 voltage sensing circuit a resistor divider is used as voltage sensor. the 660 k resistor is separated into four, 2 x 150 k and 2 x 1 8 0 k , in-series resistors, which ensure that a high voltage transient does not bypass the resistor. this also reduces the potential across the resistors, thereby decreasing the possibility of arcing. the following resistors are used to implement resistor divider: r = r13 + r2 + r3 + r4 = 660 k r5 = 470 . inductance l1 and capacitor c2 create a filter which prevents electromagnetic interference (emi). am12745v1 v c c v c c v c c v c c v c c v c c n c l k c l k d a r d a s d a t n c l k c l k n c l k c l k j 1 c a r d _ e d g e _ 1 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 1 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 1 0 j 2 c a r d _ e d g e _ 1 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 1 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 1 0 j 3 c a r d _ e d g e _ 1 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 1 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 1 0 v c c v c c v c c v c c d a n d a h n c l k c l k n c l k c l k j 5 c a r d _ e d g e _ 1 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 1 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 1 0 j 4 c a r d _ e d g e _ 1 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 1 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 1 0
AN4121 circuit description doc id 023243 rev 1 7/26 figure 4. daughterboard circuit schematic 2.2.4 jumper settings the onboard jumpers jp1 to jp4 allow the setting of the stpms2 device according to ta b l e 2 , ta b l e 3 , ta b l e 4 and ta bl e 5 below. am12799v1 table 2. precision mode and input amplifier gain selection jp1 ms0 description 1 gnd lpr, amplifier gain selection g3 = 32 2 (1) 1. default value. clk lpr, amplifier gain selection g0 = 4 3 nclk hpr, amplifier gain selection g0 = 4 4 vdd hpr, amplifier gain selection g3 = 32
AN4121 circuit description doc id 023243 rev 1 8 /26 for further details on device configuration, please refer to its datasheet. 2.3 clock management network a 4.194 mhz quartz is used to supply the clock to the stpmc1 device. to set this frequency, internal configuration bits mdiv and fr1 must be kept cleared. a synchronized clock is provided to all the stpms2 through pin clk, whose frequency is programmable through bit hsa to 1.049 mhz or 2.097 mhz. 2.4 communication with microprocessor a control board with embedded microprocessor may be connected to connector p1 using 10-wire flat cable. ta b l e 5 below describes the pinout of the connector. the stpmc1 has an spi communication port implemented by four multipurpose pins (scs, syn-np, sda-td, scl-nlc). table 3. tc of the band-gap reference jp2 ms1 description 1 gnd tc = 60 ppm/c 2 (1) 1. default value. clk flattest tc = +30 ppm/c 3 nclk tc = +160 ppm/c 4vddtc = -160 ppm/c table 4. control of voltage channel and output signals jp3 ms2 description 1 (1) 1. default value. gnd voltage channel on, datn = ~(dat =(clk) ? bsv : bsc) 2 clk voltage channel off, datn = bscn, dat = bsc 3 nclk voltage channel off, datn = bscn, dat = bsc 4 vdd voltage channel on, datn = bsc, dat = bsv table 5. changing of band-gap voltage reference jp4 ms3 description 1 (1) 1. default value. gnd hard mode, bist mode off 2clk soft mode 3 nclk reserved 4vdd hard mode, bist mode on
AN4121 circuit description doc id 023243 rev 1 9/26 in standalone operating mode these multipurpose pins output: negative power direction on syn-np pin; tamper condition detected on sda-td pin; no load condition detected on scl-nlc pin. for this reason these pins are connected to the three leds, d9, d10 and d11. in this configuration, the led pin outputs a pulse train with frequency proportional to the three-phase power and it is connected to led d12. when configured in peripheral operating mode, the spi port is enabled and some microcontroller based applications can either read internal data records or write the mode and configuration signals by means of dedicated protocol, or reset the device. by default, the stpmc1 is configured in peripheral mode (configuration bits apl=0). this also implies the following output settings: watchdog reset signal on mon pin; zero-crossing (zcr) on mop pin; programmable energy pulsed output on led pin. for further information on stpmc1 programmable bit settings, please refer to the datasheet. the stpmc1 spi protocol is explained in detail in a related application note. connector p1 is also used in the demonstration phase to connect the measurement module to a pc through the stpm parallel programmer/reader hardware interface. this allows the user to set temporary and/or permanently the internal stpmc1 registers using a dedicated gui. the votp pin on the connector p1 is used when a host wants to permanently write some configuration bits in the stpmc1 device. in this case, a +15 v power level must be present on the votp. this level must be delivered from the host itself because the module does not have an onboard charge pump. table 6. p1 connector pin description pin pin name functional description 1. votp power supply input of +15.0 v during permanent write to otp cells 2. --- not connected 3. gnd signal reference level 0 v and power supply return 4. sda-td spi interface data 5. scs spi interface enable 6. scl-nlc spi interface clock 7. --- not connected 8 . syn-np spi interface signal 9. --- not connected 10. vcc power-out of +3.3 or 5 v
AN4121 board layout doc id 023243 rev 1 10/26 3 board layout 3.1 layout rules for three-phase systems design noise rejection is the main issue to work on when a three phase multi-chip approach has been chosen. in this case layout plays a crucial role. here are some rules to follow in the layout phase of three-phase systems: component positioning the components of the measuring section (stpms2, current sensor, passive components) should be placed using the same layout for each phase. the phases should be placed in a symmetrical scheme. in this way a reduction of the cross talking can be achieved. the current sensor should be placed very close to the corresponding stpms2 to minimize the captured noise. component routing the passive components belonging to the analog input channels must be placed between the sensor and the stpms2, always respecting a symmetrical scheme. quartz the crystal network must be placed close to the stpmc1, and a completely symmetrical path from the clk pin of the stpmc1 to stpms2 devices must be ensured. a copper plate has been adopted under the crystal both on the top and on the bottom side of the pcb. grounding the stpms2 device must be grounded by the exposed pad and by pin vss, ensuring the maximum stability of ground plane by placing vias between the top and bottom ground plane. analog and digital ground must be separated. 3.2 motherboard layout figure 5. motherboard top layout
AN4121 board layout doc id 023243 rev 1 11/26 figure 6. motherboard bottom layout 3.3 daughterboard layout figure 7. daughterboard top layout
AN4121 board layout doc id 023243 rev 1 12/26 figure 8. daughterboard bottom layout
AN4121 experimental results doc id 023243 rev 1 13/26 4 experimental results the tests have been conducted on a three-phase metering demonstration board with the stpmc1 and three stpms2ls considering i nom = 5 a, v nom = 230 v, f line = 50 hz. results are referred to the full scale dynamic range of the current channel (?fs? in ta b l e 7 ), which for the sensor selected was 37.5%, or as percentage of i nom . 4.1 three-phase energy measurement accuracy 4.1.1 test with symmetrical voltages and balanced load at pf = 1 this three-phase energy measurement has been performed in the following conditions: v r = v s = v t = 230 [v rms ] i r = i s = i t = i [a rms ] p f = 1 table 7. three-phase energy measurement i [a] % of i nom [%] % of fs [%] error [%] 22,5 450% 100% 0,097% 16 320% 71% 0,076% 12 240% 53% 0,040% 10 200% 45% 0,035% 8 160% 36% -0,00 8 % 5 100% 22% 0,027% 2 40% 9% 0,035% 1 20% 4% -0,065% 0,5 10% 2% -0,0 8 7% 0,25 5% 1% -0,096% 0,1 2% 0,4% -0,0 8 7% 0,05 1% 0,2% -0,096% 0,025 0,5% 0,1% -0,096% 0,01 0,2% 0,04% -0,352% 0,005 0,1% 0,02% -0,435% 0,0025 0,05% 0,01% -0,4 8 7%
AN4121 experimental results doc id 023243 rev 1 14/26 figure 9. graph of experimental results of three-phase energy measurements 4.1.2 test with symmetrical voltages a nd balanced load at pf = 0.5 inductive and pf = 0.8 capacitive this three-phase energy measurement has been performed in the following conditions: v r = v s = v t = 230 [v rms ] i r = i s = i t = i [a rms ] pf = 0.5 ind pf = 0. 8 cap table 8. limits for class 0,2 meters: poly-phase meters with symmetrical voltages and balanced loads at pf = 1 i [a] % of i nom [%] error [%] i max - 0,2% in 100% 0,2% 0,05*in 5% 0,2% 0,0499*in 4,99% 0,4% 0,01*in 1% 0,4% am12746v1 0,076% 0,040% 0,035% -0,008% 0,027% 0,035% -0,065% -0,087% -0,096% -0,087% -0,096% -0,096% -0,352% -0,435% -0,487% -0,6% -0,5% -0,4% -0,3% -0,2% -0,1% 0,0% 0,1% 0,2% 0,3% 0,4% 0,5% 0,01% 0,10% 1,00% 10,00% 100,00% aw error [%] % of fs class 0.2 limits
AN4121 experimental results doc id 023243 rev 1 15/26 figure 10. graph of experimental results of three-phase energy measurement table 9. three-phase energy measurement - pf = 0.5 ind i [a] % of i nom [%] % of fs [%] error [%] 12 240% 53% -0,1932% 10 200% 45% -0,1449% 8 160% 36% -0,10 8 7% 5 100% 22% -0,14 8 4% 2 40% 9% -0,0971% 1 20% 4% -0,1507% 0,5 10% 2% -0,092 8 % 0,25 5% 1% -0,034 8 % 0,1 2% 0,4% -0,1739% 0,05 1% 0,2% 0,0174% table 10. three-phase energy measurement - pf = 0.8 cap i [a] % of i nom [%] % of fs [%] error [%] 12 240% 53% 0,0393% 10 200% 45% 0,0525% 8 160% 36% 0,0 8 61% 5 100% 22% 0,0362% 2 40% 9% 0,0634% 1 20% 4% 0,0435% 0,5 10% 2% 0,0362% 0,25 5% 1% 0,0652% 0,1 2% 0,4% 0,0725% 0,05 1% 0,2% 0,1 8 12% am12747v1 -0,1932% -0,1449% -0,1087% -0,1484% -0,0971% -0,1507% -0,0928% -0,0348% -0,1739% 0,0174% 0,0393% 0,0525% 0,0861% 0,0362% 0,0634% 0,0435% 0,0362% 0,0652% 0,0725% 0,1812% -0,6% -0,4% -0,2% 0,0% 0,2% 0,4% 0,6% 1% 10% 100% 1000% aw error [%] % of in class 0.2 limit - pf = 0,5l/0,8c pf = 0,8c pf = 0,5l
AN4121 experimental results doc id 023243 rev 1 16/26 4.2 typical phase energy measurement accuracy 4.2.1 test with symmetrical voltages and only one phase load at pf = 1 and pf = 0,5 inductive this single-phase energy measurement has been performed in the following conditions: v r = v s = v t = 230 [v rms ] i r = i [a rms ] i s = i t = 0 pf = 1 pf = 0.5 ind table 11. limits for class 0,2 meters: poly-phase meters with symmetrical voltages and balanced loads at pf = 0,5 ind or 0,8 cap i [a] % of i nom [%] error [%] i max - 0,3% in 100% 0,3% 0,1*in 10% 0,3% 0,099*in 9,9% 0,5% 0,02*in 5% 0,5% table 12. phase energy measurement i [a] % of in [%] error [%] 10 200% -0,0003% 8 160% -0,0212% 5 100% -0,0426% 2 40% 0,1152% 1 20% -0,0309% 0,5 10% -0,034 8 % 0,2 4% 0,1196%
AN4121 experimental results doc id 023243 rev 1 17/26 figure 11. graph of experimental results of one phase energy measurement table 13. phase energy measurement pf = 0.5 inductive i [a] % of in [%] error [%] 10 200% -0,234 8 % 8 160% -0,2565% 5 100% -0,2504% 2 40% -0,1 8 70% 1 20% -0,20 8 7% 0,5 10% -0,1217% 0,2 4% 0,0130% table 14. limits for class 0,2 meters: poly-phase meters with symmetrical voltages and only one phase load at pf = 1 i [a] % of in [%] error [%] i max 1000% 0,3% 0,05*in 5% 0,3% table 15. limits for class 0,2 meters: poly-phase meters with symmetrical voltages and only one phase load at pf = 0.5 ind i [a] % of in [%] error [%] i max 1000% 0,4% 0,1*in 10% 0,4% am12748v1 - 0,000 3% - 0,0212 % - 0,0426 % 0,1152 % - 0,0 3 09 % - 0,0 3 48 % 0,1196 % - 0,2 3 48 % - 0,2565 % - 0,2504 % - 0,1870 % - 0,2087 % - 0,1217 % 0,01 3 0 % -0,5 % -0,4 % -0, 3% -0,2 % -0,1 % 0,0 % 0,1 % 0,2 % 0, 3% 0,4 % 0,5 % 1 % 10 % 100 % 1000 % aw error [ % ] % of in cl ass 0.2 limit - pf = 0,5 cl ass 0.2 limit - pf = 1 pf = 0,5 pf = 1
AN4121 three-phase systems doc id 023243 rev 1 1 8 /26 appendix a three-phase systems three-phase is a common method of electric power transmission. it is a type of poly-phase system used to power motors and many other devices. the currents are sinusoidal functions of time, all at the same frequency but with different phases. in a three-phase system the phases are spaced equally, giving a phase separation of 120. the frequency is typically 50 hz in europe and 60 hz in the us and canada. figure 12. instantaneous voltage (or current) in one voltage cycle of a three-phase system the three phases may be supplied over six wires, with two wires reserved for the exclusive use of each phase. however, they are generally supplied over three or four wires: three-phase, 3-wire delta service which has no neutral and 220 v between phases three-phase, 4-wire delta and wye service which has 220 v between phase-neutral and 3 8 0 v phase-phase. a.1 power in three-phase ac circuits let's assume that the angle between the phase voltage and the phase current is , which is equal to the angle of the load impedance. considering the load configurations given in figure 14 , the phase power and the total power can be estimated easily.
AN4121 three-phase systems doc id 023243 rev 1 19/26 figure 13. per-phase powers in (a) a delta-connected load and (b) wye-connected load in the case of figure 13 .a , the total active power is equal to three times the power of one phase: since the line current in the balanced delta-connected loads, if this equation is substituted into equation 3.51, the total active load becomes: equation 1 in figure 13 .b , however, the impedances contain the line currents i line (equal to the phase current, i phase ) and the phase voltages: therefore, the phase active power and the total active power are: = = = = cos i v p p p p phase line 3 2 1 = = cos i v 3 p 3 p phase line total phase line i 3 i = = cos i v 3 p line line total 3 v v line phase = = = = = cos i v p p p p line phase 3 2 1 = = cos i v 3 p 3 p line phase total
AN4121 three-phase systems doc id 023243 rev 1 20/26 if the relationship between the phase voltage and the line voltage is used, the total active power becomes identical to equation 1 developed. this means that the total power in any balanced three-phase load ( - or y-connected) is given by equation 1 . similarly, the total reactive and the total apparent power in the three-phase balanced ac circuits can be given by: a.2 power measurement techniques in the three-phase power systems, one, two, or three wattmeters can be used to measure the total power. a wattmeter may be considered to be a voltmeter and an ammeter combined in the same box, which has a deflection proportional to v rms i rms cos , where is the angle between the voltage and current. hence, a wattmeter has two voltage and two current terminals, which have + or polarity signs. three power measurement methods utilizing the wattmeters are described next, and are applied to the balanced three-phase ac load. a.2.1 two-wattmeter method this method can be used in a three-phase 3-wire balanced or unbalanced load system that may be connected or y. to perform the measurement, two wattmeters are connected as shown in figure 14 . figure 14. two-wattmeter method in star- or delta-connected load in the balanced loads, the sum of the two wattmeter readings gives the total power. this can be proven in a star-connected load mathematically using the power reading of each meter as: = sin i v 3 q line line total line line total i v 3 s =
AN4121 three-phase systems doc id 023243 rev 1 21/26 if the difference of the readings is computed, which is 1/ ? 3 times the total three-phase reactive power. this means that the two- wattmeter method can also indicate the total reactive power in the three-phase loads and also the power factor. a.2.2 three-wattmeter method this method is used in a three-phase four-wire balanced or unbalanced load. the connections are made with one meter in each line as shown in figure 15 . in this configuration, the total active power supplied to the load is equal to the sum of the three wattmeter readings. figure 15. the wattmeter connections in the three-phase 4-wire loads a.2.3 one-wattmeter method this method is suitable only in three-phase 4-wire balanced loads. the connection of the wattmeter is similar to the drawing given in figure 15 . the total power is equal to three times the reading of only one wattmeter that is connected between one phase and the neutral. () ) 30 cos( i v 30 cos i v p line line 1 12 1 + = + = () ) 30 cos( i v 30 cos i v p line line 3 32 2 ? = ? = = + = cos i v 3 p p p line line 2 1 total = + ? ? = ? sin i v ) 30 cos( i v ) 30 cos( i v p p line line line line line line 1 2 3 2 1 total p p p p + + =
bom list AN4121 22/26 doc id 023243 rev 1 appendix b bom list table 16. motherboard bom list item quantity reference part pcb footprint description 1 2 c61,c62 15 p sm_0 8 05 21 c63 1 sm_0 8 05 3 1 c64 10 n sm_0 8 05 4 1 c65 100 n sm_0 8 05 5 1 c66 1000 cpcyl1_d500_ls200_040 capacitor al-rill 13x22/2m*1000my 25 v 6 2 d7 diode sm_d_1206 diode planar 1n414 8 sod323*75 v 62 d 8 diode_zener sm_d_1206 diode zener zmm sod 8 0*5.1 v (3.3 v) g 7 4 d9, d10, d11, d12 diode_led plcc2 smd led low current super red p-lcc-2 osram (distrelec 631039) 8 5 j1, j2, j3, j4, j5 card_edge_10 sullins_10_drxi 9 1 p1 morsetti_5x2 jumper_5x2_bis 10 5 r15, r16, r35, r55, r56 100 sm_0 8 05 11 4 r60, r61, r62, r63 4.7 k sm_0 8 05 12 1 r64 1m 1% sm_0 8 05 13 1 tp2 tp test_point 14 1 u 8 stpmc1 sog_65m_20_w300_l260 15 1 u9 st_m74hc14 sog_050_14_w325_l350 16 1 w2 mon test_point 17 1 w3 dah test_point 1 8 1 w4 dar test_point 19 1 w5 mop test_point 20 1 w6 das test_point 21 1 w7 dat test_point
AN4121 bom list doc id 023243 rev 1 23/26 item quantity reference part pcb footprint description 22 1 w 8 gnd test_point 23 1 w9 dan test_point 24 1 w10 clk test_point 25 1 w34 morsetti_2 morsetti_2 26 1 y1 4194.304 khz auris_hc49ussmd hc-49/us smd (distrelec 335026) table 17. daughterboard bom list item quantity reference part pcb footprint description 1 1 c1 470 n rad_1250x425_ls1075_037 capacitor x2 12x21x32/11m*470n 275 v k 2 1 c2 1 n disc_400x200_ls300x100_037 capacitor ker x1/y2 9x5/3m*1.0n 440/330 3 1 c3 22 n sm_0603 4 1 c4 10 n sm_0603 5 6 c5, c6, c11, c14 1 sm_0603 6 1 c12, c13 100 n sm_0603 74c7, c 8 , c9, c10 5 n sm_0603 8 2 d1, d2 diode_rele sm_1 8 12 diode rectifier smd*600 v 1 a 9 2 jp1, jp2 morsetti_4x2 jumper_4x2 10 1 j1 card_edge_10 card_edge_10_mirror 11 1 l1 220 sm_1 8 12 inductor vf 8 2423 1 8 12*220myh 0,1 a 12 1 r1 8 2 rad_725x200_ls300_040 resistor wire sfr051 8 p5 2w* 8 2r k 13 4 r2, r3, r4, r13 150 k 1% sm_0603 14 2 r5, r12 475 1% sm_0603 15 1 r6 3.4 1% sm_0603 16 2 r7, r 8 1 k 1% sm_0603 17 1 r9 42.2 k 1% sm_0603 table 16. motherboard bom list (continued)
AN4121 bom list doc id 023243 rev 1 24/26 item quantity reference part pcb footprint description 1 8 1 r10 2.2 m 1% sm_0603 19 1 r11 100 1% sm_0603 20 2 r14, r17 10 sm_0603 21 2 r15 or r16, r1 8 0 sm_0603 22 1 sh1 170 r_shunt 23 1 sh2 170 r_shunt_2 24 1 tr1 e4622_x503 vac_e4622_x503 25 1 u1 stpms2l mcs_manual_mlp3x3_16_05_pa d 26 1 v1 460 v disc_450x200_ls300x100_037 varistor moks k10*300v 27 1 w1 n test_point 2 8 1 w2 f test_point 29 1 w3 dar test_point 30 1 w4 vreg test_point 31 2 w5, w 8 vcc test_point 32 1 w6 gnd test_point 33 1 w7 clk test_point table 17. daughterboard bom list (continued)
AN4121 revision history doc id 023243 rev 1 25/26 5 revision history table 18. document revision history date revision changes 06-nov-2012 1 initial release.
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